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? 2005 microchip technology inc. ds21668b-page 1 mcp6141/2/3/4 features: ? low quiescent current: 600 na/amplifier (typ.) ? gain bandwidth product: 100 khz (typ.) ? stable for gains of 10 v/v or higher ? rail-to-rail input/output ? wide supply voltage range: 1.4v to 5.5v ? available in single, dual, and quad ? chip select (cs ) with mcp6143 ? available in 5-lead and 6-lead sot-23 packages ? temperature ranges: - industrial: -40c to +85c - extended: -40c to +125c applications: ? toll booth tags ? wearable products ? temperature measurement ? battery powered available tools: ? spice macro models (at www.microchip.com) ? filterlab? software (at www.microchip.com) related devices: ? mcp6041/2/3/4: unity gain stable op amps typical application description: the mcp6141/2/3/4 family of non-unity gain stable operational amplifiers (op amps) from microchip tech- nology inc. operate with a single supply voltage as low as 1.4v, while drawing less than 1 a (max.) of quies- cent current per amplifier. these devices are also designed to support rail-to-rail input and output opera- tion. this combination of features supports battery-powered and portable applications. the mcp6141/2/3/4 amplifiers have a gain bandwidth product of 100 khz (typ.) and are stable for gains of 10 v/v or higher. these specifications make these op amps appropriate for battery powered applications where a higher frequency response from the amplifier is required. the mcp6141/2/3/4 family operational amplifiers are offered in single (mcp6141), single with chip select (cs ) (mcp6143), dual (mcp6142) and quad (mcp6144) configurations. the mcp6141 device is available in the 5-lead sot-23 package, and the mcp6143 device is available in the 6-lead sot-23 package. package types mcp614x v out r f r 3 v 3 r 2 v 2 r 1 v 1 v ref inverting, summing amplifier v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc mcp6141 pdip, soic, msop mcp6142 pdip, soic, msop mcp6143 pdip, soic, msop mcp6144 pdip, soic, tssop v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc v ina + v ina ? v dd v ind ? v ind + 1 2 3 4 14 13 12 11 v ss v outd v outa v inb ? v inb + v outb v inc + v inc ? 5 6 7 10 9 8 v outc v in + v ss v in ? 1 2 3 5 4 v dd v out mcp6141 sot-23-5 v in + v ss v in ? 1 2 3 6 4 v dd v out mcp6143 sot-23-6 5 cs 600 na, non-unity gain rail-to-rail input/output op amps
mcp6141/2/3/4 ds21668b-page 2 ? 2005 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ?v ss ........................................................................7.0v all inputs and outputs .................... v ss ? 0.3v to v dd +0.3v difference input voltage ...................................... |v dd ?v ss | output short circuit current ..................................continuous current at input pins ....................................................2 ma current at output and supply pins ............................30 ma storage temperature....................................?65c to +150c junction temperature.................................................. +150c esd protection on all pins (hbm; mm) ................ 4 kv; 200v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out v dd /2, and r l = 1 m to v dd /2. parameters sym. min. typ. max. units conditions input offset input offset voltage v os -3 ? +3 mv v cm = v ss drift with temperature v os / t a ?1.5? v/c v cm = v ss , t a = -40c to +125c power supply rejection psrr 70 85 ? db v cm = v ss input bias current and impedance input bias current i b ?1?pa industrial temperature i b ? 20 100 pa t a = +85 extended temperature i b ? 1200 5000 pa t a = +125 input offset current i os ?1?pa common mode input impedance z cm ?10 13 ||6 ? ||pf differential input impedance z diff ?10 13 ||6 ? ||pf common mode common mode input range v cmr v ss ? 0.3 ? v dd +0.3 v common mode rejection ratio cmrr 62 80 ? db v dd = 5v, v cm = -0.3v to 5.3v cmrr 60 75 ? db v dd = 5v, v cm = 2.5v to 5.3v cmrr 60 80 ? db v dd = 5v, v cm = -0.3v to 2.5v open loop gain dc open loop gain (large signal) a ol 95 115 ? db r l = 50 k to v dd /2, v out = 0.1v to v dd ? 0.1v output maximum output voltage swing v ol , v oh v ss +10 ? v dd ? 10 mv r l = 50 k to v dd /2, 0.5v output overdrive linear region output voltage swing v ovr v ss + 100 ? v dd ? 100 mv r l = 50 k to v dd /2, a ol 95 db output short circuit current i sc ?2?mav dd = 1.4v i sc ?20?mav dd = 5.5v power supply supply voltage v dd 1.4 ? 5.5 v quiescent current per amplifier i q 0.3 0.6 1.0 ai o = 0
? 2005 microchip technology inc. ds21668b-page 3 mcp6141/2/3/4 ac electrical characteristics mcp6143 chip select (cs ) electrical characteristics figure 1-1: chip select (cs ) timing diagram (mcp6143 only). electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out v dd /2, r l = 1 m to v dd /2, and c l =60pf. parameters sym. min. typ. max. units conditions ac response gain bandwidth product gbwp ? 100 ? khz slew rate sr ? 24 ? v/ms phase margin pm ? 60 ? g = +10 noise input voltage noise e ni ?5.0? v p-p f = 0.1 hz to 10 hz input voltage noise density e ni ? 170 ? nv/ hz f = 1 khz input current noise density i ni ?0.6?fa/ hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out v dd /2, r l = 1 m to v dd /2, and c l =60pf. parameters sym. min. typ. max. units conditions cs low specifications cs logic threshold, low v il v ss ?v ss +0.3 v cs input current, low i csl ?5?pacs = v ss cs high specifications cs logic threshold, high v ih v dd ?0.3 ? v dd v cs input current, high i csh ?5?pacs = v dd cs input high, gnd current i ss ?-20? pacs = v dd amplifier output leakage, cs high i oleak ?20?pacs = v dd dynamic specifications cs low to amplifier output turn-on time t on ?250msg = +1v/v, cs = 0.3v to v out = 0.9v dd /2 cs high to amplifier output high-z t off ?10? sg = +1v/v, cs = v dd ?0.3v to v out = 0.1v dd /2 hysteresis v hyst ?0.6? vv dd = 5.0v v il high-z t on v ih cs t off v out -20 pa (typ.) high-z i ss i cs 5 pa (typ.) 5 pa (typ. ) -20 pa (typ. ) -0.6 a (typ.)
mcp6141/2/3/4 ds21668b-page 4 ? 2005 microchip technology inc. temperature characteristics electrical characteristics: unless otherwise indicated, v dd = +1.4v to +5.5v, v ss = gnd. parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 ? +85 c industrial temperature parts t a -40 ? +125 c extended temperature parts operating temperature range t a -40 ? +125 c (note 1) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ?256?c/w thermal resistance, 6l-sot-23 ja ?230?c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ?163?c/w thermal resistance, 8l-msop ja ?206?c/w thermal resistance, 14l-pdip ja ?70?c/w thermal resistance, 14l-soic ja ?120?c/w thermal resistance, 14l-tssop ja ?100?c/w note 1: the mcp6141/2/3/4 family of industrial temperature op amps operates over this extended range, but with reduced performance. in any case, the internal junction temperature (t j ) should not exceed the absolute maximum specification of +150c.
? 2005 microchip technology inc. ds21668b-page 5 mcp6141/2/3/4 2.0 typical performance curves note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-1: input offset voltage at v dd =1.4v. figure 2-2: input offset voltage drift at v dd =1.4v. figure 2-3: input offset voltage vs. common mode input voltage at v dd =1.4v. figure 2-4: input offset voltage at v dd =5.5v. figure 2-5: input offset voltage drift at v dd =5.5v. figure 2-6: input offset voltage vs. common mode input voltage at v dd =5.5v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% -3-2-10123 input offset voltage (mv) percentage of occurrences 1200 samples v dd = 1.4v 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -10-8-6-4-2 0 2 4 6 810 input offset voltage drift (v/c) percentage of occurrences 235 samples v dd = 1.4v t a = -40c to +125c -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 common mode input voltage (v) input offset voltage (v) v dd = 1.4v t a = +25c t a = -40c t a = +125c t a = +85c 0% 2% 4% 6% 8% 10% 12% 14% 16% -3 -2 -1 0 1 2 3 input offset voltage (mv) percentage of occurrences 1200 samples v dd = 5.5v 0% 5% 10% 15% 20% 25% 30% -10-8-6-4-20246810 input offset voltage drift (v/c) percentage of occurrences 235 samples v dd = 5.5v t a = -40c to +125c -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v t a = +25c t a = -40c t a = +125c t a = +85c
mcp6141/2/3/4 ds21668b-page 6 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-7: input offset voltage vs. output voltage. figure 2-8: input noise voltage density vs. frequency. figure 2-9: cmrr, psrr vs. frequency. figure 2-10: the mcp6141/2/3/4 family shows no phase reversal. figure 2-11: input noise voltage density vs. common mode input voltage. figure 2-12: cmrr, psrr vs. ambient temperature. 250 300 350 400 450 500 0.00.51.01.52.02.53.03.54.04.55.05.5 output voltage (v) input offset voltage (v) r l = 50 k v dd = 5.5v v dd = 1.4v 100 1,000 0.1 1 10 100 1000 frequency (hz) input noise voltage density (nv/ hz) 20 30 40 50 60 70 80 90 1 10 100 1,000 10,00 0 frequency (hz) cmrr, psrr (db) psrr? psrr+ referred to input cmrr 1 10 100 1k 10k -1 0 1 2 3 4 5 6 0 5 10 15 20 25 time (5 ms/div) input, output voltages (v) v in v dd = 5.0v g = +11 v/v v out 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input noise voltage density (nv/ hz) f = 1 khz v dd = 5.0v 70 75 80 85 90 95 100 -50 -25 0 25 50 75 100 125 ambient temperature (c) psrr, cmrr (db) psrr (v cm = v ss ) cmrr (v dd = 5.0v, v cm = -0.3v to +5.3v)
? 2005 microchip technology inc. ds21668b-page 7 mcp6141/2/3/4 note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-13: input bias, offset currents vs. ambient temperature. figure 2-14: open-loop gain, phase vs. frequency. figure 2-15: dc open-loop gain vs. power supply voltage. figure 2-16: input bias, offset currents vs. common mode input voltage. figure 2-17: dc open-loop gain vs. load resistance. figure 2-18: dc open-loop gain vs. output voltage headroom. 0.1 1 10 100 1000 10000 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias and offset currents (pa) | i os | i b v dd = 5.5v v cm = v dd 0.1 1 10 100 1k 10k -40 -20 0 20 40 60 80 100 120 1.e- 02 1.e- 01 1.e+ 00 1.e+ 01 1.e+ 02 1.e+ 03 1.e+ 04 1.e+ 05 frequency (hz) open-loop gain (db) -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () 10m 100m 1 10 100 1k 10k 100k gain phase 80 90 100 110 120 130 140 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) dc open-loop gain (db) r l = 50 k v out = 0.1v to v dd - 0.1v 0.1 1 10 100 1000 10000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (pa) t a = +85c v dd = 5.5v i b | i os | t a = +125c 0.1 1 10 100 1k 10k 60 70 80 90 100 110 120 130 1.e+02 1.e+03 1.e+04 1.e+0 5 load resistance ( ) dc open-loop gain (db) v dd = 1.4v 100 1k 10k 100k v out = 0.1v to v dd - 0.1v v dd = 5.5v 70 80 90 100 110 120 130 140 0.00 0.05 0.10 0.15 0.20 0.25 output voltage headroom; v dd ? v oh or v ol ? v ss (v) dc open-loop gain (db) r l = 50 k v dd = 5.5v v dd = 1.4v
mcp6141/2/3/4 ds21668b-page 8 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-19: channel-to-channel separation vs. frequency (mcp6142 and mcp6144 only). figure 2-20: gain bandwidth product, phase margin vs. ambient temperature at v dd =1.4v. figure 2-21: quiescent current vs. power supply voltage. figure 2-22: gain bandwidth product, phase margin vs. common mode input voltage. figure 2-23: gain bandwidth product, phase margin vs. ambient temperature at v dd =5.5v. figure 2-24: output short circuit current vs. power supply voltage. 80 90 100 110 120 130 140 1.e+03 1.e+0 4 frequency (hz) channel-to-channel separation (db) 1k 10k input referred 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 phase margin () pm (g = +10) gbwp v dd = 1.4v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current (a/amplifier) t a = +125c t a = +85c t a = +25c t a = -40c 0 10 20 30 40 50 60 70 80 90 100 110 120 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 100 110 120 phase margin () pm (g = +10) gbwp v dd = 5.0v 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 90 phase margin () pm (g = +10) gbwp v dd = 5.5v -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5 ambient temperature (c) output short circuit current (ma) t a = -40c t a = +25c t a = +25c t a = -40c t a = +85c t a = +125c
? 2005 microchip technology inc. ds21668b-page 9 mcp6141/2/3/4 note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-25: output voltage headroom vs. output current magnitude. figure 2-26: slew rate vs. ambient temperature. figure 2-27: small signal non-inverting pulse response. figure 2-28: output voltage headroom vs. ambient temperature. figure 2-29: maximum output voltage swing vs. frequency. figure 2-30: small signal inverting pulse response. 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) output voltage headroom, v dd ? v oh or v ol ? v ss (mv) v dd ? v oh v ol ? v ss 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 12 5 ambient temperature (c) slew rate (v/ms) high-to-low low-to-high v dd = 1.4v v dd = 5.5v -80 -60 -40 -20 0 20 40 60 80 0.00.10.20.30.40.50.60.70.80.91. 0 time (100 s/div) output voltage (20 mv/div) g = +11 v/v r l = 50 k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 12 5 ambient temperature (c) output voltage headroom, v dd ? v oh or v ol ? v ss (mv) v ol ? v ss v dd ? v oh v dd = 5.5v r l = 50 k 0.1 1 10 1.e+02 1.e+03 1.e+04 frequency (hz) maximum output voltage swing (v p-p ) 100 1k 10k v dd = 5.5v v dd = 1.4v -80 -60 -40 -20 0 20 40 60 80 0.00.10.20.30.40.50.60.70.80.91. 0 time (100 s/div) voltage (20 mv/div) g = -10 v/v r l = 50 k
mcp6141/2/3/4 ds21668b-page 10 ? 2005 microchip technology inc. note: unless otherwise indicated, t a = 25c, v dd = +1.4v to +5.5v, v ss = gnd, v cm =v dd /2, r l =1m to v dd /2, v out v dd /2, and c l =60pf. figure 2-31: large signal non-inverting pulse response. figure 2-32: chip select (cs ) to amplifier output response time (mcp6143 only). figure 2-33: large signal inverting pulse response. figure 2-34: internal chip select (cs ) hysteresis (mcp6143 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 00011111222 time (200 s/div) output voltage (v) v dd = 5.0v g = +11 v/v r l = 50 k 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 012345678910 time (1 ms/div) cs voltage (v) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage (v) v dd = 5.0v g = +11 v/v v in = +3.0v v out high-z on cs on 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 00011111222 time (200 s/div) output voltage (v) v dd = 5.0v g = -10 v/v r l = 50 k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00.51.01.52.02.53.03.54.04.55.0 cs voltage (v) internal cs switch output (v) v out on v out high-z v dd = 5.0v g = +11 v/v v in = 3.0v hysteresis cs high-to-low cs low-to-high
? 2005 microchip technology inc. ds21668b-page 11 mcp6141/2/3/4 3.0 pin descriptions descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high-imped- ance cmos inputs with low bias currents. 3.3 cs digital input this is a cmos, schmitt-triggered input that places the part into a low-power mode of operation. 3.4 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 1.4v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the other pins are at voltages between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these can share a bulk capacitor with nearby analog parts (within 100 mm), but it is not required. mcp6141 (pdip, soic, msop) mcp6141 (sot-23-5) mcp6142 mcp6143 (pdip, soic, msop) mcp6143 (sot-23-6) mcp6144 symbol description 611611v out ,v outa analog output (op amp a) 242242v in ?, v ina ? inverting input (op amp a) 333333v in +, v ina + non-inverting input (op amp a) 758764v dd positive power supply ?? 5?? 5v inb + non-inverting input (op amp b) ?? 6?? 6v inb ? inverting input (op amp b) ?? 7?? 7v outb analog output (op amp b) ????? 8v outc analog output (op amp c) ????? 9v inc ? inverting input (op amp c) ?????10v inc + non-inverting input (op amp c) 4244211v ss negative power supply ?????12v ind + non-inverting input (op amp d) ?????13v ind ? inverting input (op amp d) ?????14v outd analog output (op amp d) ???8 5 ?cs chip select 1, 5, 8 ? ? 1, 5 ? ? nc no internal connection
mcp6141/2/3/4 ds21668b-page 12 ? 2005 microchip technology inc. 4.0 applications information the mcp6141/2/3/4 family of op amps is manufactured using microchip?s state-of-the-art cmos process these op amps are stable for gains of 10 v/v and higher. they are suitable for a wide range of general purpose, low-power applications. see microchip?s related mcp6041/2/3/4 family of op amps for applications needing unity gain stability. 4.1 rail-to-rail inputs the mcp6141/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. figure 2-10 shows the input voltage exceed- ing the supply voltage without any phase reversal. the input stage of the mcp6141/2/3/4 op amps uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm ), while the other operates at high v cm . with this topol- ogy, the device operates with v cm tp to 0.3v above v dd and 0.3v below v ss . the input offset voltage (v os ) is measured at v cm =v ss ? 0.3v and v dd + 0.3v to ensure proper operation. input voltages that exceed the absolute maximum volt- age range (v ss ? 0.3v to v dd + 0.3v) can cause excessive current to flow into or out of the input pins. current beyond 2 ma can cause reliability problems. applications that exceed this rating must be externally limited with a resistor, as shown in figure 4-1. figure 4-1: input current-limiting resistor (r in ). 4.2 rail-to-rail output there are two specifications that describe the output swing capability of the mcp6141/2/3/4 family of op amps. the first specification (maximum output voltage swing) defines the absolute maximum swing that can be achieved under the specified load condition. thus, the output voltage swings to within 10 mv of either sup- ply rail with a 50 k load to v dd /2. figure 2-10 shows how the output voltage is limited when the input goes beyond the linear region of operation. the second specification that describes the output swing capability of these amplifiers is the linear output voltage range. this specification defines the maxi- mum output swing that can be achieved while the amplifier still operates in its linear region. to verify linear operation in this range, the large signal dc open-loop gain (a ol ) is measured at points inside the supply rails. the measurement must meet the specified a ol condition in the specification table. 4.3 output loads and battery life the mcp6141/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. there is minimal quiescent current glitch- ing when chip select (cs ) is raised or lowered. this prevents excessive current draw, and reduced battery life, when the part is turned off or on. heavy resistive loads at the output can cause exces- sive battery drain. driving a dc voltage of 2.5v across a 100 k load resistor will cause the supply current to increase by 25 a, depleting the battery 43 times as fast as i q (0.6 a, typ.) alone. high frequency signals (fast edge rate) across capaci- tive loads will also significantly increase supply current. for instance, a 0.1 f capacitor at the output presents an ac impedance of 15.9 k (1/2 fc) to a 100 hz sin- ewave. it can be shown that the average power drawn from the battery by a 5.0 v p-p sinewave (1.77 v rms ), under these conditions, is equation 4-1: this will drain the battery 18 times as fast as i q alone. 4.4 stability 4.4.1 noise gain the mcp6141/2/3/4 op amp family is designed to give high bandwidth and slew rate for circuits with high noise gain (g n ) or signal gain. low gain applications should be realized using the mcp6041/2/3/4 op amp family; this simplifies design and implementation issues. noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all other voltage sources are zeroed (shorted out). noise gain is independent of signal gain and depends only on components in the feedback loop. the amplifier circuits in figure 4-2 and figure 4-3 have their noise gain calculated as follows: r in maximum expected v in () v dd ? 2 ma ------------------------------------------------------------------------------ r in v ss minimum expected v in () ? 2 ma --------------------------------------------------------------------------- v b mcp614x r in v out r f r in v a p supply = (v dd - v ss ) (i q + v l(p-p) f c l ) = (5v)(0.6 a + 5.0v p-p 100hz 0.1f) = 3.0 w + 50 w
? 2005 microchip technology inc. ds21668b-page 13 mcp6141/2/3/4 equation 4-2: in order for the amplifiers to be stable, the noise gain should meet the specified minimum noise gain. note that a noise gain of g n = +10 v/v corresponds to a non-inverting signal gain of g = +10 v/v, or to an inverting signal gain of g = -9 v/v. figure 4-2: noise gain for non-inverting gain configuration. figure 4-3: noise gain for inverting gain configuration. figure 4-4 shows a unity gain buffer and miller integra- tor that are unstable when used with the mcp6141/2/3/4 family. note that the capacitor makes the integrator circuit reach unity gain at high frequencies, which makes these op amps unstable. figure 4-4: typical unstable circuits for the mcp6141/2/3/4 family. 4.4.2 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 60 pf when g = +10), a small series resistor at the output (r iso in figure 4-5) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the band- width will be generally lower than the bandwidth with no capacitive load. figure 4-5: output resistor, r iso stabilizes large capacitive loads. figure 4-6 gives recommended r iso values for differ- ent capacitive loads and gains. the x-axis is the nor- malized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -9 v/v gives g n = +10 v/v). figure 4-6: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso ?s value until the response is reasonable. bench evaluation and simula- tions with the mcp6141/2/3/4 spice macro model are helpful. g n 1 r f r g ------ - 10 v/v + = v in mcp614x r in v out r f r g mcp614x r in v out r f r g v in mcp614x v out v in mcp614x v out c r v in unity gain buffer miller integrator v b mcp614x r iso v out c l r f r g v a 1,000 10,000 100,000 1.e+00 1.e+01 1.e+02 1.e+03 normalized load capacitance; c l /g n (f) recommended r iso ( : : ) 1p 1k 100k 10p g n = +10 g n = +20 g n t t +50 10k 1n 100p
mcp6141/2/3/4 ds21668b-page 14 ? 2005 microchip technology inc. 4.5 mcp6143 chip select (cs ) the mcp6143 is a single op amp with chip select (cs ). when cs is pulled high, the supply current drops to 50 na (typ.) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high impedance state. by pulling cs low, the amplifier is enabled. if the cs pin is left floating, the amplifier may not operate properly. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.6 supply bypass with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high frequency performance. it can use a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor is not required for most applications and can be shared with other nearby analog parts. 4.7 unused op amps an unused op amp in a quad package (mcp6144) should be configured as shown in figure 4-7. these circuits prevent the output from toggling and causing crosstalk. circuits a and b are set near the minimum noise gain. circuit a can use any reference voltage between the supplies, provides a buffered dc voltage, and minimizes the supply current draw of the unused op amp. circuit b may draw a little more supply current for the unused op amp. circuit c uses the minimum number of components and operates as a comparator; it may draw more current than either circuit a or b. figure 4-7: unused op amps. 4.8 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow, which is greater than the mcp6141/2/3/4 family?s bias current at 25c (1 pa, typ.). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-8. figure 4-8: example guard ring layout for inverting gain. 1. non-inverting gain and unity gain buffer: a) connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b) connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 2. inverting gain and trans-impedance gain (con- vert current to voltage, such as photo detectors) amplifiers: a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. v dd v dd v dd ? mcp6144 (a) ? mcp6144 (b) r r 15r r r 10r v dd ? mcp6144 (c) guard ring v in ?v in +
? 2005 microchip technology inc. ds21668b-page 15 mcp6141/2/3/4 4.9 application circuits 4.9.1 battery current sensing the mcp6141/2/3/4 op amps? common mode input range, which goes 0.3v beyond both supply rails, sup- ports their use in high side and low side battery current sensing applications. the very low quiescent current (0.6 a, typ.) help prolong battery life, and the rail-to-rail output supports detection low currents. figure 4-9 shows a high side battery current sensor circuit. the 1 k resistor is sized to minimize power losses. the battery current (i dd ) through the 1 k resistor causes its top terminal to be more negative than the bottom terminal. this keeps the common mode input voltage of the op amp at v dd , which is within its allowed range. when no current is flowing, the output will be at its maximum output voltage swing (v oh ), which is virtually at v dd . . figure 4-9: high side battery current sensor. 4.9.2 inverting summing amplifier the mcp6141/2/3/4 op amp is well suited for the inverting summing amplifier shown in figure 4-10 when the resistors at the input (r 1 , r 2 , and r 3 ) make the noise gain at least 10 v/v. the output voltage (v out ) is a weighted sum of the inputs (v 1 , v 2 , and v 3 ), and is shifted by the v ref input. the necessary calculations follow in equation 4-3. . figure 4-10: summing amplifier. equation 4-3: v dd i dd v dd v ss mcp6141 1k 100 k v ss 1m 1.4v to 5.5v v out mcp614x v out r f r 3 v 3 r 2 v 2 r 1 v 1 v ref g n 1r f 1 r 1 ----- - 1 r 2 ----- - 1 r 3 ----- - ++ ?? ?? 10 v/v + = noise gain: output signal: v out v 1 g 1 v 2 g 2 v 3 g 3 v ref g n +++ = g 1 r f r 1 ? ? = signal gains: g 2 r f r 2 ? ? = g 3 r f r 3 ? ? =
mcp6141/2/3/4 ds21668b-page 16 ? 2005 microchip technology inc. 5.0 design tools microchip provides the basic design tools needed for the mcp6141/2/3/4 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6141/2/3/4 op amps is available on our web site at www.micro- chip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation at room temperature. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software the filterlab software is an innovative tool that simplifies analog active filter (using op amps) design. it is available free of charge from our web site at www.microchip.com. the filterlab software tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance.
? 2005 microchip technology inc. ds21668b-page 17 mcp6141/2/3/4 6.0 packaging information 6.1 package marking information 8-lead msop example : xxxxxx ywwnnn 6143i 536256 5-lead sot-23 ( mcp6141 ) example: xxnn as25 device e-temp code mcp6141 asnn note: applies to 5-lead sot-23 6-lead sot-23 ( mcp6143) example: xxnn aw25 device e-temp code mcp6143 awnn note: applies to 6-lead sot-23 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
mcp6141/2/3/4 ds21668b-page 18 ? 2005 microchip technology inc. package marking information (continued) 14-lead pdip (300 mil) ( mcp6144 )example : xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn mcp6144 -i/p 0434256 xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example : 8-lead soic (150 mil) example : xxxxxxxx xxxxyyww nnn mcp6141 i/p256 0223 mcp6142 i/sn0223 256 mcp6141 e/p 256 0536 mcp6142e sn 0536 256 mcp6144 0536256 3 e or or 3 e i/p 3 e or
? 2005 microchip technology inc. ds21668b-page 19 mcp6141/2/3/4 package marking information (continued) 14-lead tssop ( mcp6144 ) example : 14-lead soic (150 mil) ( mcp6144 ) example: xxxxxxxxxx yywwnnn xxxxxxxx yyww nnn 6144st 0534 256 xxxxxxxxxx mcp6144isl 0434256 mcp6144 0536256 i/sl ^^ or 3 e 6144est 0534 256 or
mcp6141/2/3/4 ds21668b-page 20 ? 2005 microchip technology inc. 5-lead plastic small outline transistor (ot) (sot-23) 1 p d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 f foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: eiaj equivalent: sc-74a drawing no. c04-091 * controlling parameter revised 09-12-05
? 2005 microchip technology inc. ds21668b-page 21 mcp6141/2/3/4 6-lead plastic small outline transistor (ch) (sot-23) 1 d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 bsc .075 bsc p1 outside lead pitch 0.95 bsc .038 bsc p pitch 6 6 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: jeita (formerly eiaj) equivalent: sc-74a * controlling parameter drawing no. c04-120 bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m revised 09-12-05
mcp6141/2/3/4 ds21668b-page 22 ? 2005 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) d a a1 l c a2 e1 e p b n1 2 f dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per s ide. .037 ref f footprint (reference) notes: revised 07-21-05 * controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 bsc .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters * 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 - - - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - -- bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. see asme y14.5m see asme y14.5m drawing no. c04-111
? 2005 microchip technology inc. ds21668b-page 23 mcp6141/2/3/4 8-lead plastic dual in-line (p) ? 300 mil body (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches * millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-001 drawing no. c04-018 significant characteristic
mcp6141/2/3/4 ds21668b-page 24 ? 2005 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches * millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-001 drawing no. c04-018 significant characteristic
? 2005 microchip technology inc. ds21668b-page 25 mcp6141/2/3/4 14-lead plastic dual in-line (p) ? 300 mil body (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches * millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
mcp6141/2/3/4 ds21668b-page 26 ? 2005 microchip technology inc. 14-lead plastic small outline (sl) ? narrow, 150 mil body (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
? 2005 microchip technology inc. ds21668b-page 27 mcp6141/2/3/4 14-lead plastic thin shrink small outline (st) ? 4.4 mm body (tssop) l c 2 1 d n b p e1 e a2 a1 a 8 4 0 8 4 0 foot angle mold draft angle bottom 12 ref mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 1.05 1.00 .043 .041 .039 a overall height 0.65 bsc .026 bsc p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters * inches units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per si de. notes: jedec equivalent: mo-153 ab-1 revised: 08-17-05 * controlling parameter bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. see asme y14.5m see asme y14.5m drawing no. c04-087 12 ref 12 ref 12 ref
mcp6141/2/3/4 ds21668b-page 28 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21668b-page 29 mcp6141/2/3/4 appendix a: revision history revision b (november 2005) the following is the list of modifications: 1. added the following: a) sot-23-5 package for the mcp6141 single op amps. b) sot-23-6 package for the mcp6143 single op amps with chip select. c) extended temperature (-40c to +125c) op amps. 2. updated specifications in section 1.0 ?electri- cal characteristics? for e-temp parts. 3. corrected and updated plots in section 2.0 ?typical performance curves? . 4. added section 3.0 ?pin descriptions? . 5. updated section 4.0 ?applications informa- tion? and added section on unused op amps. 6. updated section 5.0 ?design tools? to include filterlab. 7. added sot-23-5 and sot-23-6 packages and corrected package marking information in section 6.0 ?packaging information? . 8. added appendix a: ?revision history? . revision a (september 2002) ? original release of this document.
mcp6141/2/3/4 ds21668b-page 30 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21668b-page 31 mcp6141/2/3/4 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6141: single op amp mcp6141t: single op amp (tape and reel for sot-23, soic, msop) mcp6142: dual op amp mcp6142t: dual op amp (tape and reel for soic and msop) mcp6143: single op amp w/ cs mcp6143t: single op amp w/ cs (tape and reel for sot-23, soic, msop) mcp6144: quad op amp mcp6144t: quad op amp (tape and reel for soic and tssop) temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: ch = plastic small outline transistor (sot-23), 6-lead (tape and reel - mcp6143 only) ms = plastic micro small outline (msop), 8-lead ot = plastic small outline transistor (sot-23), 5-lead (tape and reel - mcp6141 only) p = plastic dip (300 mil body), 8-lead, 14-lead sl = plastic soic (150 mil body), 14-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm body), 14-lead examples: a) mcp6141-i/p: industrial temp., 8ld pdip package. b) mcp6141t-e/ot: tape and reel, extended temp., 5ld sot-23 package. a) mcp6142-i/sn: industrial temp., 8ld soic package. b) mcp6142t-e/ms: tape and reel, extended temp., 8ld msop package. a) mcp6143-i/p: industrial temp., 8ld pdip package. b) mcp6143t-e/ch: tape and reel, extended temp., 6ld sot-23 package. a) mcp6144-i/sl: industrial temp., 14ld pdip package. b) mcp6144t-e/st: tape and reel, extended temp., 14ld tssop package. part no. device - x temperature / xx package range
mcp6141/2/3/4 ds21668b-page 32 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21668b-page 33 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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